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ARC: Application-Level Refinement and Cache Mapping for Performance Optimization on the Edge

 
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cris.virtual.orcid0009-0005-5094-5701
cris.virtual.orcid0000-0002-0029-6548
cris.virtual.orcid0000-0002-3599-8515
cris.virtualsource.department0aba5169-585a-4a10-8bbd-7c7e93dac604
cris.virtualsource.departmentf6f17b49-e3c3-4223-9429-3bcd739eacc2
cris.virtualsource.department7a992f6f-feea-493d-b4d8-c297450cff52
cris.virtualsource.orcid0aba5169-585a-4a10-8bbd-7c7e93dac604
cris.virtualsource.orcidf6f17b49-e3c3-4223-9429-3bcd739eacc2
cris.virtualsource.orcid7a992f6f-feea-493d-b4d8-c297450cff52
dc.contributor.authorKatsaragakis, Manolis
dc.contributor.authorLamprakos, Christos
dc.contributor.authorKourzanov, Peter
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorPapadopoulos, Lazaros
dc.contributor.authorCatthoor, Francky
dc.contributor.authorSoudris, Dimitrios
dc.date.accessioned2026-06-03T07:33:58Z
dc.date.available2026-06-03T07:33:58Z
dc.date.createdwos2026-02-10
dc.date.issued2025
dc.description.abstractRecent advances in applications that are highly dependent on efficient cache utilization, in addition to the rapid growth of Edge computing systems deployed with emerging processors, generate a complex paradigm across the hardware and software continuum. In this work, we propose ARC, a novel systematic exploration methodology for application-level refinement and cache configuration mapping over emerging architectures for performance optimization. More specifically, our solution relies on workload partitioning and source code slicing mechanisms aiming to boost co-exploration of cache configuration parameters. Our proposed methodology is evaluated on a real-life IoT biomedical use case deployed over GEM5 RISC-V simulated system, showing that i) the co-impact of source code refinement and effective cache configuration leads to 61.1% execution time optimization, ii) the effective application organization and refinement leads to reduced hardware complexity. Last, we provide guidelines for application cache-friendly source code organization for performance optimization.
dc.description.wosFundingTextThis work has been partially funded by EU Horizon program CONVOLVE under grant agreement No 101070374 (https://convolve.eu).
dc.identifier.doi10.1109/iscas56072.2025.11044229
dc.identifier.isbn979-8-3503-5684-7
dc.identifier.issn0271-4302
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59512
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Symposium on Circuits and Systems (ISCAS)
dc.source.conferencedate2025-05-25
dc.source.conferencelocationLondon
dc.source.journal2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS
dc.source.numberofpages5
dc.title

ARC: Application-Level Refinement and Cache Mapping for Performance Optimization on the Edge

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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