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Litho-process-litho for 2D 32nm hp LOGIC and DRAM double patterning
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Litho-process-litho for 2D 32nm hp LOGIC and DRAM double patterning
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Date
2010
Proceedings Paper
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19018.pdf
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Wong, Patrick
;
Wiaux, Vincent
;
Verhaegen, Staf
;
Vandenbroeck, Nadia
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Abstract
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1904
since deposited on 2021-10-19
1
last month
Acq. date: 2025-12-15
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Metrics
Views
1904
since deposited on 2021-10-19
1
last month
Acq. date: 2025-12-15
Citations