Publication:
Ultrathin (< 4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits
Date
| dc.contributor.author | Green, Martin | |
| dc.contributor.author | Gusev, E. P. | |
| dc.contributor.author | Degraeve, Robin | |
| dc.contributor.author | Garfunkel, E. L. | |
| dc.contributor.imecauthor | Degraeve, Robin | |
| dc.date.accessioned | 2021-10-14T16:59:14Z | |
| dc.date.available | 2021-10-14T16:59:14Z | |
| dc.date.issued | 2001 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/5321 | |
| dc.source.beginpage | 2057 | |
| dc.source.endpage | 2121 | |
| dc.source.issue | 5 | |
| dc.source.journal | Journal of Applied Physics | |
| dc.source.volume | 90 | |
| dc.title | Ultrathin (< 4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
| Publication available in collections: |