Co-Optimized Double-Exposure Stitching with ILT to Maximize High-NA EUV Process Window

Abstract

Upcoming generations of integrated circuits (e.g., below the 14 angstrom device node) will be achieved with the help of anamorphic optics in high-NA EUV scanners. Layers exposed on high-NA anamorphic scanners will require two or more stitched mask exposures to achieve the equivalent exposure area of previous-generation scanners. In this paper we show examples of how simultaneous co-optimization of stitched exposures & masks using ILT can improve resolution, process window, edge-placement error, mask rule check limitations and design rule restrictions of real design patterns in advanced high-NA EUV processes with stitched exposure fields. These results show improvement for the negative effects of double exposure processes in mask manufacturing, main feature wafer pattern fidelity, traditional sub-resolution assist features and stray light reducing sub-resolution grid feature placement. We also describe how co-optimized stitching ILT can help minimize overlay sensitivity via overlay-aware ILT mask co-optimization in the stitch region. We also make comparisons of ILT single exposure and stitched mask optimization to more traditional single-segment solver model-based optical proximity correction for complex stitching logic layouts and corner cases from parametric test patterns.