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Exploring ESD challenges in sub-20-nm bulk FinFET CMOS technology nodes

Date

2013
Proceedings Paper
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dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHellings, Geert
dc.contributor.authorThijs, Steven
dc.contributor.authorLinten, Dimitri
dc.contributor.authorScholz, Mirko
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorThijs, Steven
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecThijs, Steven::0000-0003-2889-8345
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.date.accessioned2021-10-21T06:55:55Z
dc.date.available2021-10-21T06:55:55Z
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/22127
dc.source.beginpage1
dc.source.conference35th Annual EOS/ESD Symposium
dc.source.conferencedate8/09/2013
dc.source.conferencelocationLas Vegas, NV USA
dc.source.endpage8
dc.title

Exploring ESD challenges in sub-20-nm bulk FinFET CMOS technology nodes

dc.typeProceedings paper
dspace.entity.typePublication
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