PPAT for Multi-Die 3D Accelerator Design in Advanced Nanosheet and CFET Technology

Abstract

In this paper, we demonstrate that Multi-Plane Systolic Arrays (MP-SAs) can execute workloads in up to 2× less compute cycles than conventional Single-Plane SAs (SP-SAs), given the same compute capacity. However, increasing the number of processing planes in a 2D-IC implementation introduces interconnect overheads. Deploying MP-SAs in multi-die 3D-ICs using advanced CMOS technology reduces interconnect by up to 30%, but results in only a 5% reduction in power consumption, mostly dominated by logic. Nevertheless, for a workload that shows 30% less compute cycles, MP-SAs in 3D-ICs can achieve 17% higher energy efficiency when compared to their SP-SAs counterparts implemented as 2D-IC. Finally, despite increased power density, we demonstrate that thermal challenges can be effectively managed with appropriate cooling strategies, even in 4-Dies 3D-IC configurations.