Publication:

Edge placement error analysis for N7 logic patterning options

Date

2015
Proceedings Paper
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dc.contributor.authorvan Setten, Eelco
dc.contributor.authorPsara, Eleni
dc.contributor.authorWittebrood, Friso
dc.contributor.authorOorschot, Dorothe
dc.contributor.authorvan Dijk, Joep
dc.contributor.authorSchiffelers, Guido
dc.contributor.authorFinders, Jo
dc.contributor.authorDusa, Mircea
dc.contributor.authorPhilipsen, Vicky
dc.contributor.authorHendrickx, Eric
dc.contributor.imecauthorSchiffelers, Guido
dc.contributor.imecauthorDusa, Mircea
dc.contributor.imecauthorPhilipsen, Vicky
dc.contributor.imecauthorHendrickx, Eric
dc.contributor.orcidimecPhilipsen, Vicky::0000-0002-2959-432X
dc.contributor.orcidimecHendrickx, Eric::0000-0003-2516-0417
dc.date.accessioned2021-10-23T00:17:32Z
dc.date.available2021-10-23T00:17:32Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26089
dc.source.conferenceInternational Symposium on Extreme Ultraviolet Lithography - EUVL
dc.source.conferencedate5/10/2015
dc.source.conferencelocationMaastricht Netherlands
dc.title

Edge placement error analysis for N7 logic patterning options

dc.typeProceedings paper
dspace.entity.typePublication
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