Publication:
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime
| dc.contributor.author | Dargupally, Mahipal | |
| dc.contributor.author | Acharya, Lomash Chandra | |
| dc.contributor.author | Singh, Khoirom Johnson | |
| dc.contributor.author | Gupta, Neha | |
| dc.contributor.author | Sharma, Arvind | |
| dc.contributor.author | Dasgupta, Sudeb | |
| dc.contributor.author | Bulusu, Anand | |
| dc.contributor.imecauthor | Sharma, Arvind | |
| dc.contributor.orcidimec | Sharma, Arvind::0000-0003-1188-4924 | |
| dc.date.accessioned | 2024-08-29T13:43:57Z | |
| dc.date.available | 2024-07-28T19:32:32Z | |
| dc.date.available | 2024-08-29T13:43:57Z | |
| dc.date.issued | 2024 | |
| dc.description.wosFundingText | This work was supported by the DST Science and Engineering Research Board (SERB), Government of India (GO through IMP RINT2 under Grant No. IMP/2018/001 1.58/IT. | |
| dc.identifier.doi | 10.1109/APCCAS60141.2023.00034 | |
| dc.identifier.eisbn | 979-8-3503-8119-1 | |
| dc.identifier.issn | 2837-4576 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/44208 | |
| dc.publisher | IEEE COMPUTER SOC | |
| dc.source.beginpage | 105 | |
| dc.source.conference | Asia Pacific Conference on Circuits and Systems (APCCAS) | |
| dc.source.conferencedate | NOV 19-22, 2023 | |
| dc.source.conferencelocation | Hyderabad | |
| dc.source.endpage | 109 | |
| dc.source.journal | N/A | |
| dc.source.numberofpages | 5 | |
| dc.subject.keywords | LOGICAL EFFORT | |
| dc.title | An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
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