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Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells

Date

2018
Proceedings Paper
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dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorSherazi, Yasser
dc.contributor.authorJang, Doyoung
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorBaert, Rogier
dc.contributor.authorMertens, Hans
dc.contributor.authorMattii, Luca
dc.contributor.authorParvais, Bertrand
dc.contributor.authorMocuta, Anda
dc.contributor.authorVerkest, Diederik
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.imecauthorJang, Doyoung
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorBaert, Rogier
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-25T18:52:54Z
dc.date.available2021-10-25T18:52:54Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/30745
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8510633
dc.source.beginpage143
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate18/06/2018
dc.source.conferencelocationHonolulu, HI USA
dc.source.endpage144
dc.title

Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells

dc.typeProceedings paper
dspace.entity.typePublication
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