Unraveling BTI in IGZO devices: impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions

Abstract

We study the impact of the device architecture, channel deposition method, stoichiometry and phase, and AC stress on the BTI of IGZO thinfilm transistors fabricated on 300-mm wafers. Two main conclusions are obtained. First, reliability of IGZO based devices is strongly architecture dependent, and therefore reliability solutions are not universal. Second, top-gate (TG) devices are more severely impacted by the abnormal negative ΔVth during PBTI at T>25∘C, ascribed to a H-doping process, than back-gated (BG) counterparts. Two remedies for the negative ΔVth are identified: In-poor films (In~5%) and AC stress with duty-cycle< <25% do not reveal signs of H-doping process within the experimental time window, and thus are promising for reliable product operation.