Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients

dc.contributor.author	Sharma, Arvind
dc.contributor.author	Madhusudan, Meghna
dc.contributor.author	Burns, Steven M.
dc.contributor.author	Yaldiz, Soner
dc.contributor.author	Mukherjee, Parijat
dc.contributor.author	Harjani, Ramesh
dc.contributor.author	Sapatnekar, Sachin S.
dc.contributor.imecauthor	Sharma, Arvind
dc.contributor.orcidimec	Sharma, Arvind::0000-0003-1188-4924
dc.date.accessioned	2025-06-04T08:40:51Z
dc.date.available	2024-12-03T16:44:53Z
dc.date.available	2025-06-04T08:40:51Z
dc.date.issued	2024
dc.description.wosFundingText	This work was supported in part by the DARPA IDEA program, as part of the ALIGN Project, SPAWAR under Contract N660011824048, and in part by the Semiconductor Research Corporation under Grant 2810.083.
dc.identifier.doi	10.1109/TCAD.2024.3402988
dc.identifier.issn	0278-0070
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/44906
dc.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage	4373
dc.source.endpage	4385
dc.source.issue	12
dc.source.journal	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
dc.source.numberofpages	13
dc.source.volume	43
dc.title	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients
dc.type	Journal article
dspace.entity.type	Publication
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