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Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing

 
dc.contributor.authorCaselli, Michele
dc.contributor.authorSubhechha, Subhali
dc.contributor.authorDebacker, Peter
dc.contributor.authorMallik, Arindam
dc.contributor.authorVerkest, Diederik
dc.contributor.imecauthorCaselli, Michele
dc.contributor.imecauthorSubhechha, Subhali
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorMallik, Arindam
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecSubhechha, Subhali::0000-0002-1960-5136
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecMallik, Arindam::0000-0002-0742-9366
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2023-06-15T12:27:03Z
dc.date.available2023-04-29T04:11:25Z
dc.date.available2023-06-15T12:27:03Z
dc.date.issued2022
dc.identifier.doi10.1109/ISCAS48785.2022.9937962
dc.identifier.eisbn978-1-6654-8485-5
dc.identifier.issn0271-4302
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41494
dc.publisherIEEE
dc.source.beginpage1462
dc.source.conferenceIEEE International Symposium on Circuits and Systems (ISCAS)
dc.source.conferencedateMAY 28-JUN 01, 2022
dc.source.conferencelocationAustin
dc.source.endpage1466
dc.source.journalna
dc.source.numberofpages5
dc.title

Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing

dc.typeProceedings paper
dspace.entity.typePublication
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