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Deterministic and stochastic component in RESET transient of HfSiO/FUSI gate RRAM stack

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dc.contributor.authorDegraeve, Robin
dc.contributor.authorGoux, Ludovic
dc.contributor.authorRoussel, Philippe
dc.contributor.authorWouters, Dirk
dc.contributor.authorKittl, Jorge
dc.contributor.authorAltimime, Laith
dc.contributor.authorJurczak, Gosia
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorGoux, Ludovic
dc.contributor.imecauthorRoussel, Philippe
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecGoux, Ludovic::0000-0002-1276-2278
dc.contributor.orcidimecRoussel, Philippe::0000-0002-0402-8225
dc.date.accessioned2021-10-19T13:11:28Z
dc.date.available2021-10-19T13:11:28Z
dc.date.embargo9999-12-31
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18819
dc.source.beginpage28
dc.source.conferenceSymposium on VLSI Technology
dc.source.conferencedate13/06/2011
dc.source.conferencelocationJapan Kyoto
dc.source.endpage30
dc.title

Deterministic and stochastic component in RESET transient of HfSiO/FUSI gate RRAM stack

dc.typeProceedings paper
dspace.entity.typePublication
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