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Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits

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dc.contributor.authorSchram, Tom
dc.contributor.authorSutar, Surajit
dc.contributor.authorRadu, Iuliana
dc.contributor.authorAsselberghs, Inge
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorSutar, Surajit
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorAsselberghs, Inge
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecSutar, Surajit::0000-0003-3114-718X
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.contributor.orcidimecAsselberghs, Inge::0000-0001-8371-3222
dc.date.accessioned2023-01-05T13:21:58Z
dc.date.available2022-09-13T02:51:20Z
dc.date.available2022-12-02T08:42:08Z
dc.date.available2023-01-05T13:21:58Z
dc.date.embargo2022-09-07
dc.date.issued2022-12-01
dc.description.wosFundingTextThis work was done in the imec IIAP core CMOS programs. This work received funding from the European Union's Graphene Flagship grant agreement No 952792. The authors also thank COVENTOR for the access to the SEMulator3D software, and specifically Assawer Sousou for the technical support. The authors also thank the entire IMEC 2D project team for the discussions preceding the preparation if the paper.
dc.identifier.doi10.1002/adma.202109796
dc.identifier.issn0935-9648
dc.identifier.pmidMEDLINE:36071023
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40421
dc.publisherWILEY-V C H VERLAG GMBH
dc.source.beginpage2109796
dc.source.endpage2109796
dc.source.issue48
dc.source.journalADVANCED MATERIALS
dc.source.numberofpages13
dc.source.volume34
dc.subject.disciplineElectrical & electronic engineering
dc.subject.keywordsintegration
dc.subject.keywordsMoS2
dc.subject.keywordsMX2
dc.subject.keywordstransition metal dichalcogenides
dc.subject.keywordswafer-scale
dc.subject.keywordsWS2
dc.title

Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits

dc.typeJournal article
dspace.entity.typePublication
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