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Double patterning EDA solutions for the 32nm HP and beyond

Date

2007
Proceedings Paper
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dc.contributor.authorBailey, George
dc.contributor.authorTritchkov, Alexander
dc.contributor.authorPark, Jea-Woo
dc.contributor.authorHong, Le
dc.contributor.authorWiaux, Vincent
dc.contributor.authorHendrickx, Eric
dc.contributor.authorVerhaegen, Staf
dc.contributor.authorXie, Peng
dc.contributor.authorVersluijs, Janko
dc.contributor.imecauthorWiaux, Vincent
dc.contributor.imecauthorHendrickx, Eric
dc.contributor.imecauthorVersluijs, Janko
dc.date.accessioned2021-10-16T15:01:45Z
dc.date.available2021-10-16T15:01:45Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11678
dc.identifier.urlww.spie.org
dc.source.beginpage65211k
dc.source.conferenceDesign for Manufacturability through Design-Process Integration
dc.source.conferencedate28/02/2007
dc.source.conferencelocationSan Jose, CA USA
dc.title

Double patterning EDA solutions for the 32nm HP and beyond

dc.typeProceedings paper
dspace.entity.typePublication
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