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Characterization of Interface States in CVD Monolayer MoS<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> MOS Capacitors via the Conductance Method

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtualsource.department94e90e9c-c0f2-483e-ab8b-6f9590d5fec9
cris.virtualsource.orcid94e90e9c-c0f2-483e-ab8b-6f9590d5fec9
dc.contributor.authorNakamura, Shiho
dc.contributor.authorLin, Zaoyang
dc.contributor.authorTsuruoka, Daiki
dc.contributor.authorEndo, Takahiko
dc.contributor.authorYu, Xiao
dc.contributor.authorLee, Tsung-En
dc.contributor.authorMiyata, Yasumitsu
dc.contributor.authorAoki, Nobuyuki
dc.contributor.authorKe, Mengnan
dc.date.accessioned2026-09-14T13:57:24Z
dc.date.available2026-09-14T13:57:24Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractMoS2 is one of the transition metal dichalcogenides (TMDCs) that has been extensively studied as a next-generation semiconductor material due to its high carrier mobility in the monolayer limit. However, the atomically thin nature of MoS2 poses challenges for capacitance characteristics measurements by metal-oxide-semiconductor (MOS) capacitors, leading to limited research on the characteristics of their interfaces. In this study, we fabricated MOS capacitors with different device areas using a monolayer MoS2synthesized by chemical vapor deposition and Al2O3 insulator deposited by atomic layer deposition and performed capacitance-voltage measurements. We propose the use of a ring-shaped capacitor which is beneficial for small 2D crystals such as exfoliated TMDCs or materials that cannot yet be synthesized on a large scale, and extracted interface trap densities on the order of 1012 eV −1 cm −2 for devices with different areas, indicating that under the present measurement conditions, series and access resistances do not dominate the extraction of interface trap density using the conductance method.
dc.description.wosFundingTextThis work was supported in part by Japan Science and Technology Agency (JST), in part by PRESTO under Grant JPMJPR24H2, in part by Japan Society for the Promotion of Science (JSPS) KAKENHI under Grant 23K13361, in part by Tokyo Electron Ltd., and in part by the Kenjiro Takayanagi Foundation and Iketani Science and Technology Foundation.
dc.identifier.doi10.1109/led.2026.3708092
dc.identifier.eissn1558-0563
dc.identifier.issn0741-3106
dc.identifier.issn1558-0563
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60366
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage1720
dc.source.endpage1723
dc.source.issue9
dc.source.journalIEEE ELECTRON DEVICE LETTERS
dc.source.numberofpages4
dc.source.volume47
dc.subject.keywordsLAYER
dc.subject.keywordsTRANSISTORS
dc.title

Characterization of Interface States in CVD Monolayer MoS2/Al2O3 MOS Capacitors via the Conductance Method

dc.typeJournal article
dspace.entity.typePublication
imec.internal.crawledAt2026-07-04
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-11
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