Publication:
Characterization of Interface States in CVD Monolayer MoS<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> MOS Capacitors via the Conductance Method
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtualsource.department | 94e90e9c-c0f2-483e-ab8b-6f9590d5fec9 | |
| cris.virtualsource.orcid | 94e90e9c-c0f2-483e-ab8b-6f9590d5fec9 | |
| dc.contributor.author | Nakamura, Shiho | |
| dc.contributor.author | Lin, Zaoyang | |
| dc.contributor.author | Tsuruoka, Daiki | |
| dc.contributor.author | Endo, Takahiko | |
| dc.contributor.author | Yu, Xiao | |
| dc.contributor.author | Lee, Tsung-En | |
| dc.contributor.author | Miyata, Yasumitsu | |
| dc.contributor.author | Aoki, Nobuyuki | |
| dc.contributor.author | Ke, Mengnan | |
| dc.date.accessioned | 2026-09-14T13:57:24Z | |
| dc.date.available | 2026-09-14T13:57:24Z | |
| dc.date.createdwos | 2026 | |
| dc.date.issued | 2026 | |
| dc.description.abstract | MoS2 is one of the transition metal dichalcogenides (TMDCs) that has been extensively studied as a next-generation semiconductor material due to its high carrier mobility in the monolayer limit. However, the atomically thin nature of MoS2 poses challenges for capacitance characteristics measurements by metal-oxide-semiconductor (MOS) capacitors, leading to limited research on the characteristics of their interfaces. In this study, we fabricated MOS capacitors with different device areas using a monolayer MoS2synthesized by chemical vapor deposition and Al2O3 insulator deposited by atomic layer deposition and performed capacitance-voltage measurements. We propose the use of a ring-shaped capacitor which is beneficial for small 2D crystals such as exfoliated TMDCs or materials that cannot yet be synthesized on a large scale, and extracted interface trap densities on the order of 1012 eV −1 cm −2 for devices with different areas, indicating that under the present measurement conditions, series and access resistances do not dominate the extraction of interface trap density using the conductance method. | |
| dc.description.wosFundingText | This work was supported in part by Japan Science and Technology Agency (JST), in part by PRESTO under Grant JPMJPR24H2, in part by Japan Society for the Promotion of Science (JSPS) KAKENHI under Grant 23K13361, in part by Tokyo Electron Ltd., and in part by the Kenjiro Takayanagi Foundation and Iketani Science and Technology Foundation. | |
| dc.identifier.doi | 10.1109/led.2026.3708092 | |
| dc.identifier.eissn | 1558-0563 | |
| dc.identifier.issn | 0741-3106 | |
| dc.identifier.issn | 1558-0563 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/60366 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |
| dc.source.beginpage | 1720 | |
| dc.source.endpage | 1723 | |
| dc.source.issue | 9 | |
| dc.source.journal | IEEE ELECTRON DEVICE LETTERS | |
| dc.source.numberofpages | 4 | |
| dc.source.volume | 47 | |
| dc.subject.keywords | LAYER | |
| dc.subject.keywords | TRANSISTORS | |
| dc.title | Characterization of Interface States in CVD Monolayer MoS2/Al2O3 MOS Capacitors via the Conductance Method | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-07-04 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-09-11 | |
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