Optimization of Alignment Model and Metrology During Backside EUV Lithography Patterning for CFET Technology

Abstract

In a complementary field-effect transistor (CFET) technology, the complementary nMOS (metal-oxide semiconductor) and pMOS transistors are stacked on top of each other to save surface area and increase the area density. There are many challenges in such a 3D-stacked CFET manufacturing which bring up the need to develop new techniques for CFET to be viable in high volume manufacturing (HVM). Backside (BS) extreme ultraviolet (EUV) lithography is one of these many challenges, requiring tight overlay control across the wafer. In this article, we investigated different alignment models during high order corrections per exposure (HOCPE) in BS EUV lithography. We demonstrated the overview of the capability of different alignment model and its density, metrology density and time, and the achievable overlay (as low as <4 nm) with the associated trade-off. Altogether, we exhibited the controllability of BS overlay corrections and feasibility to aid the process to be prepared and possibly ported to HVM.