Publication:

3.5T CFET Block-Level DTCO for Superior PPA in A7 Node by Split Power, hDR Cells, Optimized Pins and BEOL

Date

2025
Proceedings Paper
https://doi.org/10.1109/iedm50572.2025.11353539
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dc.contributor.authorLin, Ji-Yung
dc.contributor.authorKükner, Halil
dc.contributor.authorYang, Sheng
dc.contributor.authorVerschueren, Lynn
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorDell Atti, Francesco
dc.contributor.authorFarokhnejad, Anita
dc.contributor.authorVan de Put, Maarten
dc.contributor.authorZografos, Odysseas
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorHellings, Geert
dc.contributor.authorRyckaert, Julien
dc.date.accessioned2026-07-15T14:05:01Z
dc.date.available2026-07-15T14:05:01Z
dc.date.createdwos2026
dc.date.issued2025
dc.description.abstractComplementary FETs (CFET), with the structure of stacked n-/p-FETs, hold promises for continuing shrinking device footprints after the nanosheet era. To realize CFET block-level designs with superior power-performance-area (PPA), several enhancements are introduced through design technology co-optimization (DTCO), such as a double-row split-power CFET structure, half-height double-row cells, as well as optimization in pins and back-end-of-line (BEOL). Results show that A7 3.5T CFET designs reach -46% area and iso-performance compared to N2 nanosheet designs.
dc.description.wosFundingTextThis work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit nanoic-project.eu.
dc.identifier.doi10.1109/iedm50572.2025.11353539
dc.identifier.isbn979-8-3315-6786-6
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59846
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedate2025-12-06
dc.source.conferencelocationSan Francisco
dc.source.journal2025 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

3.5T CFET Block-Level DTCO for Superior PPA in A7 Node by Split Power, hDR Cells, Optimized Pins and BEOL

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-07-14
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-07-14
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