Publication:

Overview of bias temperature instability in scaled DRAM logic for memory transistors

Date

2020
Journal article
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dc.contributor.authorO'Sullivan, Barry
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorDentoni Litta, Eugenio
dc.contributor.authorSimoen, Eddy
dc.contributor.authorMachkaoutsan, Vladimir
dc.contributor.authorFazan, Pierre
dc.contributor.authorJi, Yunhyuck
dc.contributor.authorCheolygu, Kim
dc.contributor.authorSpessot, Alessio
dc.contributor.authorLinten, Dimitri
dc.contributor.authorHoriguchi, Naoto
dc.contributor.imecauthorO'Sullivan, Barry
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorDentoni Litta, Eugenio
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorMachkaoutsan, Vladimir
dc.contributor.imecauthorFazan, Pierre
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecO'Sullivan, Barry::0000-0002-9036-8241
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-29T01:41:41Z
dc.date.available2021-10-29T01:41:41Z
dc.date.issued2020
dc.identifier.issn1530-4388
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35687
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9044835?source=authoralert
dc.source.beginpage258
dc.source.endpage268
dc.source.issue2
dc.source.journalIEEE Transactions on Device and Materials Reliability
dc.source.volume20
dc.title

Overview of bias temperature instability in scaled DRAM logic for memory transistors

dc.typeJournal article
dspace.entity.typePublication
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