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A 69-dB SNDR 300-MS/s two-time interleaved pipelined SAR ADC in 16-nm CMOS FinFET with capacitive reference stabilization

Date

2018
Journal article
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dc.contributor.authorMartens, Ewout
dc.contributor.authorHershberg, Benjamin
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorMartens, Ewout
dc.contributor.imecauthorHershberg, Benjamin
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-25T23:05:13Z
dc.date.available2021-10-25T23:05:13Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31300
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8281465/
dc.source.beginpage1161
dc.source.endpage1171
dc.source.issue4
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.volume53
dc.title

A 69-dB SNDR 300-MS/s two-time interleaved pipelined SAR ADC in 16-nm CMOS FinFET with capacitive reference stabilization

dc.typeJournal article
dspace.entity.typePublication
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