Publication:

Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node

Date

2024
Proceedings Paper
https://doi.org/10.1109/iedm50854.2024.10873524
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dc.contributor.authorKükner, Halil
dc.contributor.authorMirabelli, Gioele
dc.contributor.authorYang, Sheng
dc.contributor.authorVerschueren, Lynn
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorLin, Ji-Yung
dc.contributor.authorAbdi, Dawit
dc.contributor.authorFarokhnejad, Anita
dc.contributor.authorZografos, Odysseas
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorHellings, Geert
dc.contributor.authorRyckaert, Julien
dc.date.accessioned2026-04-21T07:42:02Z
dc.date.available2026-04-21T07:42:02Z
dc.date.createdwos2026-03-18
dc.date.issued2024
dc.description.abstractComplementary FET (CFET) device architecture with stacked n-/p-FETs is an outstanding option, promising power, performance, area scalability in the post-FinFET device era. Among several options, the double-row (DR) CFET architecture leads to reduced process complexity in the middle-of-line (MOL), and gains in logic and SRAM area, by scaling to 3.5Tracks x CPP per 2 FETs. Projections show ~40% area and ~12% power scaling potential.
dc.identifier.doi10.1109/iedm50854.2024.10873524
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59135
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedate2024-12-07
dc.source.conferencelocationSan Francisco
dc.source.journal2024 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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