Publication:
Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology
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| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-3220-8856 | |
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| dc.contributor.author | Sakui, Koji | |
| dc.contributor.author | Garbin, Daniele | |
| dc.contributor.author | Iwata, Yoshihisa | |
| dc.contributor.author | Gaddemane, Gautam | |
| dc.contributor.author | Li, Yisuo | |
| dc.contributor.author | Wan, Yiqun | |
| dc.contributor.author | Kanazawa, Kenichi | |
| dc.contributor.author | Demir, Eyup Can | |
| dc.contributor.author | Kunishima, Iwao | |
| dc.contributor.author | Fantini, Andrea | |
| dc.contributor.author | Kakumu, Masakazu | |
| dc.contributor.author | Lorant, Christophe | |
| dc.contributor.author | Harada, Nozomu | |
| dc.date.accessioned | 2026-05-11T08:04:48Z | |
| dc.date.available | 2026-05-11T08:04:48Z | |
| dc.date.createdwos | 2025-10-01 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | Dynamic Flash Memory (DFM) have been fabricated on 300 mm SOI wafers with 65 nm technology, experimentally validating a wide "1" and "0" margin for the first time. The proposed device operates exclusively with positive polarity signals, eliminating the need for negative voltages. Thanks to its unique split-gate structure, a long retention time of over 10 seconds at 85 ℃, and a robust Bit Line (BL) disturbance time of 10 ms with the BL stress voltage (VSBL) of 2.5 V are demonstrated. | |
| dc.identifier.doi | 10.1109/imw61990.2025.11026959 | |
| dc.identifier.isbn | 979-8-3503-6299-2 | |
| dc.identifier.issn | 2330-7978 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59384 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.beginpage | 161 | |
| dc.source.conference | IEEE International Memory Workshop (IMW) | |
| dc.source.conferencedate | 2025-05-18 | |
| dc.source.conferencelocation | Monterey | |
| dc.source.endpage | 164 | |
| dc.source.journal | 2025 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW | |
| dc.source.numberofpages | 4 | |
| dc.title | Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-04-07 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-04-07 | |
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