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Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology

 
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dc.contributor.authorSakui, Koji
dc.contributor.authorGarbin, Daniele
dc.contributor.authorIwata, Yoshihisa
dc.contributor.authorGaddemane, Gautam
dc.contributor.authorLi, Yisuo
dc.contributor.authorWan, Yiqun
dc.contributor.authorKanazawa, Kenichi
dc.contributor.authorDemir, Eyup Can
dc.contributor.authorKunishima, Iwao
dc.contributor.authorFantini, Andrea
dc.contributor.authorKakumu, Masakazu
dc.contributor.authorLorant, Christophe
dc.contributor.authorHarada, Nozomu
dc.date.accessioned2026-05-11T08:04:48Z
dc.date.available2026-05-11T08:04:48Z
dc.date.createdwos2025-10-01
dc.date.issued2025
dc.description.abstractDynamic Flash Memory (DFM) have been fabricated on 300 mm SOI wafers with 65 nm technology, experimentally validating a wide "1" and "0" margin for the first time. The proposed device operates exclusively with positive polarity signals, eliminating the need for negative voltages. Thanks to its unique split-gate structure, a long retention time of over 10 seconds at 85 ℃, and a robust Bit Line (BL) disturbance time of 10 ms with the BL stress voltage (VSBL) of 2.5 V are demonstrated.
dc.identifier.doi10.1109/imw61990.2025.11026959
dc.identifier.isbn979-8-3503-6299-2
dc.identifier.issn2330-7978
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59384
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.beginpage161
dc.source.conferenceIEEE International Memory Workshop (IMW)
dc.source.conferencedate2025-05-18
dc.source.conferencelocationMonterey
dc.source.endpage164
dc.source.journal2025 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW
dc.source.numberofpages4
dc.title

Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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