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Sub-threshold SRAM design in 14 Nm FinFET technology with improved access time and leakage power

Date

2015
Proceedings Paper
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dc.contributor.authorZenali, Behzad
dc.contributor.authorMadsen, JK
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorMoradi, Farshad
dc.date.accessioned2021-10-23T01:29:20Z
dc.date.available2021-10-23T01:29:20Z
dc.date.embargo9999-12-31
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26231
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7309541
dc.source.beginpage74
dc.source.conferenceIEEE Computer Society Annual Symposium on VLSI - ISVLSI
dc.source.conferencedate1/05/2015
dc.source.conferencelocationMontpellier France
dc.source.endpage79
dc.title

Sub-threshold SRAM design in 14 Nm FinFET technology with improved access time and leakage power

dc.typeProceedings paper
dspace.entity.typePublication
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