Publication:

Novel dual layer floating gate structure as enabler of fully planar flash memory

Date

2010
Proceedings Paper
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dc.contributor.authorBlomme, Pieter
dc.contributor.authorRosmeulen, Maarten
dc.contributor.authorCacciato, Antonio
dc.contributor.authorKostermans, Maarten
dc.contributor.authorVrancken, Christa
dc.contributor.authorVan Aerde, Steven
dc.contributor.authorSchram, Tom
dc.contributor.authorDebusschere, Ingrid
dc.contributor.authorJurczak, Gosia
dc.contributor.authorVan Houdt, Jan
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.imecauthorVrancken, Christa
dc.contributor.imecauthorVan Aerde, Steven
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorDebusschere, Ingrid
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.accessioned2021-10-18T15:21:55Z
dc.date.available2021-10-18T15:21:55Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16756
dc.source.beginpage129
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate15/06/2010
dc.source.conferencelocationHonolulu, HI USA
dc.source.endpage130
dc.title

Novel dual layer floating gate structure as enabler of fully planar flash memory

dc.typeProceedings paper
dspace.entity.typePublication
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