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Framework for Augmenting Main Memory with CXL-connected Emerging Memory Alternatives

 
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cris.virtual.orcid0000-0002-3663-7439
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dc.contributor.authorAkhunov, Khakim
dc.contributor.authorBiswas, Dwaipayan
dc.contributor.authorKarimov, Emil
dc.contributor.authorSharma, Arvind
dc.contributor.authorOh, Hyungrock
dc.contributor.authorRosmeulen, Maarten
dc.contributor.authorRyckaert, Julien
dc.contributor.authorMyers, James
dc.date.accessioned2026-06-08T13:25:24Z
dc.date.available2026-06-08T13:25:24Z
dc.date.createdwos2026-02-10
dc.date.issued2025
dc.description.abstractThe rapid evolution of memory technologies and the advent of Compute Express Link (CXL) have opened up new possibilities for scaling main memory by enabling hybrid memory systems with pooled and shared content. System-level evaluation of new memory systems during the early development stage is important for the enablement and further integration of new memory and interconnect technologies. However, existing solutions do not offer a framework neither for emerging memory protocols nor for novel memory technologies. This paper introduces CXL-HMEM to evaluate emerging CXL-based hybrid main memory architectures by applying the System Technology Co-Optimization (STCO) technique. The framework provides flexible performance metrics, workload simulation, and memory traffic analysis to assess system performance under various hybrid memory configurations, including DRAM and tiered memory hierarchies. Key features include support for memory technologies such as IGZO-based DRAM (IGZO) and FeRAM, workload scalability, and an integrated model of the CXL behavior. CXL-HMEM shows that emerging memories can improve system bandwidth and energy consumption by 7%, while having potential to further mitigate particular bottlenecks. CXL-based hybrid main memory can speed up the memory access time by >2× compared to conventional approaches of main memory extension.
dc.identifier.doi10.1109/iscas56072.2025.11043992
dc.identifier.isbn979-8-3503-5684-7
dc.identifier.issn0271-4302
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59628
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Symposium on Circuits and Systems (ISCAS)
dc.source.conferencedate2025-05-25
dc.source.conferencelocationLondon
dc.source.journal2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS
dc.source.numberofpages5
dc.title

Framework for Augmenting Main Memory with CXL-connected Emerging Memory Alternatives

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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