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3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
Publication:
3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
Date
2011
Journal article
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21094.pdf
1.19 MB
Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Civale, Yann
;
Sabuncuoglu Tezcan, Deniz
;
Philipsen, Harold
;
Duval, Fabrice
;
Jaenen, Patrick
;
Travaly, Youssef
;
Soussan, Philippe
;
Swinnen, Bart
;
Beyne, Eric
Journal
IEEE Transactions on Components, Packaging and Manufacturing Technology
Abstract
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1993
since deposited on 2021-10-19
3
last month
2
last week
Acq. date: 2025-12-08
Citations
Metrics
Views
1993
since deposited on 2021-10-19
3
last month
2
last week
Acq. date: 2025-12-08
Citations