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The impact of energy barrier height on border traps in III-V gate stacks

Date

2015
Proceedings Paper
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dc.contributor.authorYoshida, S.
dc.contributor.authorTaniguchi, S.
dc.contributor.authorMinari, Hideki
dc.contributor.authorLin, Dennis
dc.contributor.authorIvanov, Tsvetan
dc.contributor.authorWatanabe, H.
dc.contributor.authorNakazawa, Masashi
dc.contributor.authorCollaert, Nadine
dc.contributor.authorThean, Aaron
dc.contributor.imecauthorLin, Dennis
dc.contributor.imecauthorIvanov, Tsvetan
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecIvanov, Tsvetan::0000-0003-3407-2742
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-23T01:23:36Z
dc.date.available2021-10-23T01:23:36Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26220
dc.source.beginpage75
dc.source.conferenceExtended Abstracts of International Workshop on Dielectric Thin Films for Future Electron Devices - IWDTF
dc.source.conferencedate2/11/2015
dc.source.conferencelocationTokyo Japan
dc.source.endpage76
dc.title

The impact of energy barrier height on border traps in III-V gate stacks

dc.typeProceedings paper
dspace.entity.typePublication
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