Publication:

NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware

Date

2023
Journal article
https://doi.org/10.1109/TETC.2023.3238708
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dc.contributor.authorBalaji, Adarsha
dc.contributor.authorHuynh, Phu Khanh
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDutt, Nikil D.
dc.contributor.authorKrichmar, Jeffrey L.
dc.contributor.authorDas, Anup
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2023-08-09T13:23:42Z
dc.date.available2023-07-04T20:27:21Z
dc.date.available2023-07-05T13:03:56Z
dc.date.available2023-08-09T13:23:42Z
dc.date.embargo9999-12-31
dc.date.issued2023
dc.description.wosFundingTextThis work was supported in part by the U.S. Department of Energy under Grant DE-SC0022014, in part by the National Science Foundation Award under Grant CCF-1937419 (RTML: Small: Design of System Software to Facilitate Real-Time Neuromorphic Computing) and in part by the National Science Foundation Faculty Early Career Development Award under Grant CCF-1942697 (CAREER: Facilitating Dependable Neuromorphic Computing: Vision, Architecture, and Impact on Programmability).
dc.identifier.doi10.1109/TETC.2023.3238708
dc.identifier.issn2168-6750
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42123
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage373
dc.source.endpage387
dc.source.issue2
dc.source.journalIEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
dc.source.numberofpages15
dc.source.volume11
dc.subject.keywordsNETWORK-ON-CHIP
dc.subject.keywordsSEGMENTED BUS
dc.subject.keywordsDESIGN
dc.subject.keywordsCOMMUNICATION
dc.subject.keywordsEXPLORATION
dc.subject.keywordsNEURONS
dc.subject.keywordsENERGY
dc.subject.keywordsNOC
dc.title

NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware

dc.typeJournal article
dspace.entity.typePublication
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