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A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS

Date

2010
Proceedings Paper
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dc.contributor.authorBorremans, Jonathan
dc.contributor.authorVengattaramane, Kameswaran
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-18T15:23:48Z
dc.date.available2021-10-18T15:23:48Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16776
dc.source.beginpage417
dc.source.conferenceIEEE Radio Frequency Integrated Circuits Conference - RFIC
dc.source.conferencedate23/05/2010
dc.source.conferencelocationAnaheim, CA USA
dc.source.endpage420
dc.title

A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS

dc.typeProceedings paper
dspace.entity.typePublication
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