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A 2.6mW 6b 2.2GS/s 4-times interleaved fully-dynamic pipelined ADC in 40nm digital CMOS

Date

2010
Proceedings Paper
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dc.contributor.authorVerbruggen, Bob
dc.contributor.authorCraninckx, Jan
dc.contributor.authorKuijk, Maarten
dc.contributor.authorWambacq, Piet
dc.contributor.authorVan der Plas, Geert
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.date.accessioned2021-10-18T23:40:18Z
dc.date.available2021-10-18T23:40:18Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18258
dc.source.beginpage296
dc.source.conferenceIEEE International Solid-State Circuits Conference - ISSCC
dc.source.conferencedate7/02/2010
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage297
dc.title

A 2.6mW 6b 2.2GS/s 4-times interleaved fully-dynamic pipelined ADC in 40nm digital CMOS

dc.typeProceedings paper
dspace.entity.typePublication
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