Publication:

Identifying sources of overlay error in FinFET technology

Date

2005
Proceedings Paper
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dc.contributor.authorLaidler, David
dc.contributor.imecauthorLaidler, David
dc.contributor.orcidimecLaidler, David::0000-0003-4055-3366
dc.date.accessioned2021-10-16T02:43:59Z
dc.date.available2021-10-16T02:43:59Z
dc.date.embargo9999-12-31
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10740
dc.source.beginpage80
dc.source.conferenceMetrology, Inspection, and Process Control for Microlithography XIX
dc.source.conferencedate27/02/2005
dc.source.conferencelocationSan Jose, CA USA
dc.source.endpage90
dc.title

Identifying sources of overlay error in FinFET technology

dc.typeProceedings paper
dspace.entity.typePublication
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