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Impact of device architecture and gate stack processing on the low-frequency noise of silicon nanowire transistors
Publication:
Impact of device architecture and gate stack processing on the low-frequency noise of silicon nanowire transistors
Date
2019
Proceedings Paper
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42253.pdf
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Simoen, Eddy
;
Oliveira, Alberto Vinicius
;
Veloso, Anabela
;
Vaisman Chasin, Adrian
;
Ritzenthaler, Romain
;
Mertens, Hans
;
Horiguchi, Naoto
;
Claeys, Cor
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Abstract
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1844
since deposited on 2021-10-27
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item.page.metrics.field.last-week
Acq. date: 2025-10-25
Citations
Metrics
Views
1844
since deposited on 2021-10-27
456
item.page.metrics.field.last-week
Acq. date: 2025-10-25
Citations