Publication:

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Date

2021

Proceedings Paper

https://doi.org/10.1109/iedm19574.2021.9720528

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Author(s)

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Sisto, Giuliano

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;

Hiblot, Gaspard

;

Stucchi, Michele

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Kakarla, Naveen

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Salahuddin, Shairfe Muhammad

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Schleicher, Filip

;

Veloso, Anabela

;

Hellings, Geert

;

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Milojevic, Dragomir

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Van der Plas, Geert

;

Ryckaert, Julien

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Journal

na

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1674 since deposited on 2022-07-09

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Acq. date: 2026-08-10