Publication:

Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows

Date

2015
Proceedings Paper
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dc.contributor.authorDe Vos, Joeri
dc.contributor.authorStucchi, Michele
dc.contributor.authorJourdain, Anne
dc.contributor.authorBeyne, Eric
dc.contributor.authorPatel, Jash
dc.contributor.authorCrook, Kath
dc.contributor.authorCarruthers, Mark
dc.contributor.authorHopkins, Janet
dc.contributor.authorAshraf, Huma
dc.contributor.imecauthorDe Vos, Joeri
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorJourdain, Anne
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecDe Vos, Joeri::0000-0002-9332-9336
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.accessioned2021-10-22T18:53:09Z
dc.date.available2021-10-22T18:53:09Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25157
dc.source.beginpage1
dc.source.conference17th Electronics Packaging Technology Conference - EPTC
dc.source.conferencedate2/12/2015
dc.source.conferencelocationSingapore Singapore
dc.source.endpage4
dc.title

Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows

dc.typeProceedings paper
dspace.entity.typePublication
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