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A 48-dB DR 80-MHz BW 8.88-GS/s bandpass delta-sigma ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

Date

2011
Proceedings Paper
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dc.contributor.authorMartens, Ewout
dc.contributor.authorBourdoux, André
dc.contributor.authorCouvreur, Aissa
dc.contributor.authorVan Wesemael, Peter
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorCraninckx, Jan
dc.contributor.authorRyckaert, Julien
dc.contributor.imecauthorMartens, Ewout
dc.contributor.imecauthorBourdoux, André
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecBourdoux, André::0000-0002-9264-7850
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.accessioned2021-10-19T16:05:35Z
dc.date.available2021-10-19T16:05:35Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19391
dc.source.beginpage40
dc.source.conferenceSymposium on VLSI Circuits
dc.source.conferencedate13/06/2011
dc.source.conferencelocationKyoto Japan
dc.source.endpage41
dc.title

A 48-dB DR 80-MHz BW 8.88-GS/s bandpass delta-sigma ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

dc.typeProceedings paper
dspace.entity.typePublication
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