Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

dc.contributor.author	Fan, Xin
dc.contributor.author	Stuijt, Jan
dc.contributor.author	Liu, Bo
dc.contributor.author	Gemmeke, Tobias
dc.contributor.imecauthor	Stuijt, Jan
dc.contributor.orcidimec	Stuijt, Jan::0000-0001-6797-2339
dc.date.accessioned	2021-10-27T09:08:38Z
dc.date.available	2021-10-27T09:08:38Z
dc.date.embargo	9999-12-31
dc.date.issued	2019
dc.identifier.issn	1549-8328
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/32949
dc.identifier.url	https://ieeexplore.ieee.org/document/8493543
dc.source.beginpage	941
dc.source.endpage	954
dc.source.issue	3
dc.source.journal	IEEE Transactions on Circuits and Systems I Regular Papers
dc.source.volume	66
dc.title	Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT
dc.type	Journal article
dspace.entity.type	Publication
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