Location-Aware Error Correction for Mitigating the Impact of Interconnects on STT-MRAM Reliability

Abstract

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing memory technologies. However, STT-MRAM faces reliability challenges, primarily due to stochastic switching characteristics, process variation, and manufacturing defects. Furthermore, these reliability challenges worsen as technology scales down due to the increasing dominance of interconnect parasitic resistive-capacitive (RC) effects. We propose an efficient location-aware error-correcting code (ECC)-based strategy for mitigating the impact of interconnect parasitics on STT-MRAM bit-cell reliability. By applying a non-uniform error correction mechanism across different memory zones, our approach increases correction strength with distance from the driver. The proposed approach avoids the need for uniformly strong error correction across the whole memory zone, thereby reducing ECC parity bit memory overhead while improving the reliability in the vulnerable memory zone. Furthermore, the proposed strategy has a negligible effect on system performance, as measured by instructions per cycle (IPC).