Publication:
Micro-architectural optimization of a coarse-crained array based baseband processor
Date
| dc.contributor.author | Vander Aa, Tom | |
| dc.contributor.author | Hartmann, Matthias | |
| dc.contributor.author | Raghavan, Praveen | |
| dc.contributor.author | Dejonghe, Antoine | |
| dc.contributor.author | Van der Perre, Liesbet | |
| dc.contributor.imecauthor | Vander Aa, Tom | |
| dc.contributor.imecauthor | Hartmann, Matthias | |
| dc.contributor.orcidimec | Vander Aa, Tom::0000-0002-1504-5266 | |
| dc.contributor.orcidimec | Hartmann, Matthias::0000-0001-6248-1151 | |
| dc.date.accessioned | 2021-10-18T23:21:15Z | |
| dc.date.available | 2021-10-18T23:21:15Z | |
| dc.date.issued | 2010-10 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/18217 | |
| dc.source.conference | IEEE Workshop on Signal Processing Systems - SiPS | |
| dc.source.conferencedate | 6/10/2010 | |
| dc.source.conferencelocation | Cupertino, CA USA | |
| dc.title | Micro-architectural optimization of a coarse-crained array based baseband processor | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | ||
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