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Hybrid floating gate cell for sub-20-nm NAND flash memory technology

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dc.contributor.authorBlomme, Pieter
dc.contributor.authorCacciato, Antonio
dc.contributor.authorWellekens, Dirk
dc.contributor.authorBreuil, Laurent
dc.contributor.authorRosmeulen, Maarten
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorLocorotondo, Sabrina
dc.contributor.authorVrancken, Christa
dc.contributor.authorRichard, Olivier
dc.contributor.authorDebusschere, Ingrid
dc.contributor.authorVan Houdt, Jan
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorWellekens, Dirk
dc.contributor.imecauthorBreuil, Laurent
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorLocorotondo, Sabrina
dc.contributor.imecauthorVrancken, Christa
dc.contributor.imecauthorRichard, Olivier
dc.contributor.imecauthorDebusschere, Ingrid
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecBreuil, Laurent::0000-0003-2869-1651
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.accessioned2021-10-20T10:06:44Z
dc.date.available2021-10-20T10:06:44Z
dc.date.embargo9999-12-31
dc.date.issued2012
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20369
dc.source.beginpage333
dc.source.endpage335
dc.source.issue3
dc.source.journalIEEE Electron Device Letters
dc.source.volume33
dc.title

Hybrid floating gate cell for sub-20-nm NAND flash memory technology

dc.typeJournal article
dspace.entity.typePublication
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