Publication:

A Novel DTCO-driven 1T1R Bitcell for sub-10ns STT-MRAM LLC Macros at N12 Node

 
dc.contributor.authorGarcia Redondo, Fernando
dc.contributor.authorVerschueren, Lynn
dc.contributor.authorRao, Siddharth
dc.contributor.authorPandey, Priyanka
dc.contributor.authorAbdi, Dawit
dc.contributor.authorWeckx, Pieter
dc.contributor.authorCouet, Sebastien
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorHellings, Geert
dc.contributor.imecauthorVerschueren, L.
dc.contributor.imecauthorRao, S.
dc.contributor.imecauthorPandey, P.
dc.contributor.imecauthorAbdi, D.
dc.contributor.imecauthorWeckx, P.
dc.contributor.imecauthorCouet, S.
dc.contributor.imecauthorGarcia-Bardon, M.
dc.contributor.imecauthorHellings, G.
dc.date.accessioned2025-02-02T17:54:00Z
dc.date.available2025-02-02T17:54:00Z
dc.date.issued2024
dc.identifier.doi10.1109/ESSERC62670.2024.10719478
dc.identifier.eisbn979-8-3503-8813-8
dc.identifier.isbn979-8-3503-8814-5
dc.identifier.issn1930-8833
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45143
dc.publisherIEEE
dc.source.beginpage665
dc.source.conference50th IEEE European Solid-State Electronics Research Conference (ESSERC)
dc.source.conferencedate2024-09-29
dc.source.conferencelocationBruges
dc.source.endpage668
dc.source.numberofpages4
dc.title

A Novel DTCO-driven 1T1R Bitcell for sub-10ns STT-MRAM LLC Macros at N12 Node

dc.typeProceedings paper
dspace.entity.typePublication
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