A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

Abstract

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to overcome signal degradation due to capacitive charge sharing. By exploring gm cell design and time-differential bipolar readout, we demonstrate the feasibility of 3-D stacking up to 128 FeCAPs while maintaining sub- μs access, transcending the conventional charge-sharing-defined stacking limit of 64 and achieving an effective bit density of ∼200 Mb/mm2 . Using a two-stage Miller-compensated high-GBW operational transconductance amplifier (OTA) implementation, we additionally underscore the robustness of our sensing scheme against variability in CMOS circuits, but also in bit-cell FeCAPs, such as FeCAP area variation (~80%), memory window fluctuation (~15 aF), and work function asymmetry (~200 mV). The proposed architecture further provides a flexible design tradeoff between read speed and energy consumption, where a single-stage low-power OTA design allows read energy scaling down to ~10 pJ/bit at μs -level access time. The FeCAP model is calibrated to experimental data, ensuring realistic simulation fidelity. These results offer instrumental insights into the design-technology co-optimization (DTCO) of 3-D FeRAM-based storage-class memories (SCMs).