Publication:

A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

Date

2025
Journal article
https://doi.org/10.1109/JSSC.2024.3424264
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dc.contributor.authorChen, Wen-Chieh
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHuang, Man-Ching
dc.contributor.authorChang, Shu-Wei
dc.contributor.authorHellings, Geert
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorChen, Wen-Chieh
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHuang, Man-Ching
dc.contributor.imecauthorChang, Shu-Wei
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecChen, Wen-Chieh::0000-0002-1298-6693
dc.contributor.orcidimecChen, Shih-Hung::0000-0002-6481-2951
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.date.accessioned2025-04-30T09:54:10Z
dc.date.available2024-08-05T18:18:29Z
dc.date.available2025-04-30T09:54:10Z
dc.date.issued2025
dc.identifier.doi10.1109/JSSC.2024.3424264
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44270
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage615
dc.source.endpage625
dc.source.issue2
dc.source.journalIEEE JOURNAL OF SOLID-STATE CIRCUITS
dc.source.numberofpages11
dc.source.volume60
dc.subject.keywordsVOLTAGE I/O BUFFER
dc.subject.keywordsCMOS
dc.subject.keywordsDRIVER
dc.title

A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

dc.typeJournal article
dspace.entity.typePublication
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