Publication:
Test-architecture optimization for TSV-based 3D stacked ICs
Date
| dc.contributor.author | Noia, Brandon | |
| dc.contributor.author | Goel, Sandeep Kumar | |
| dc.contributor.author | Chakrabarty, Krishnendu | |
| dc.contributor.author | Marinissen, Erik Jan | |
| dc.contributor.author | Verbree, Jouke | |
| dc.contributor.imecauthor | Marinissen, Erik Jan | |
| dc.contributor.orcidimec | Marinissen, Erik Jan::0000-0002-5058-8303 | |
| dc.date.accessioned | 2021-10-18T19:39:33Z | |
| dc.date.available | 2021-10-18T19:39:33Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/17707 | |
| dc.identifier.url | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5512787 | |
| dc.source.beginpage | 24 | |
| dc.source.conference | IEEE European Test Symposium - ETS | |
| dc.source.conferencedate | 24/05/2010 | |
| dc.source.conferencelocation | Prague Czech Republic | |
| dc.source.endpage | 29 | |
| dc.title | Test-architecture optimization for TSV-based 3D stacked ICs | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | ||
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