Publication:

Trade-off analysis between gm/I-D and f(T) of nanosheet NMOS transistors with different metal gate stack at high temperature

 
dc.contributor.authorSilva, Vanessa C. P. A.
dc.contributor.authorMartino, Joao A.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorVeloso, Anabela
dc.contributor.authorAgopian, Paula G. D.
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.accessioned2022-12-01T10:02:21Z
dc.date.available2022-05-10T02:20:05Z
dc.date.available2022-12-01T10:02:21Z
dc.date.issued2022
dc.description.wosFundingTextThe authors acknowledge CNPq and CAPES for the financial support. S. Barraud for the discussions and imec for providing the nanosheet transistors that have been processed in the frame of imec's Core Partner Program on Logic Devices.
dc.identifier.doi10.1016/j.sse.2022.108267
dc.identifier.issn0038-1101
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39783
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD
dc.source.beginpage108267
dc.source.endpagena
dc.source.issuena
dc.source.journalSOLID-STATE ELECTRONICS
dc.source.numberofpages8
dc.source.volume191
dc.subject.keywordsMOSFET
dc.title

Trade-off analysis between gm/I-D and f(T) of nanosheet NMOS transistors with different metal gate stack at high temperature

dc.typeJournal article
dspace.entity.typePublication
Files
Publication available in collections: