Publication:

Heat-path layout technique for thermal mitigation in advanced CMOS technologies

Date

2025-APR
Journal article
https://doi.org/10.1016/j.sse.2024.109054
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtualsource.department69a83b1b-e83f-42b4-afb5-5189331192f2
cris.virtualsource.orcid69a83b1b-e83f-42b4-afb5-5189331192f2
dc.contributor.authorJin, Minhyun
dc.contributor.imecauthorJin, Minhyun
dc.date.accessioned2025-01-24T18:25:50Z
dc.date.available2025-01-24T18:25:50Z
dc.date.issued2025-APR
dc.identifier.doi10.1016/j.sse.2024.109054
dc.identifier.issn0038-1101
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45106
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD
dc.source.beginpage109054
dc.source.issueApril
dc.source.journalSOLID-STATE ELECTRONICS
dc.source.numberofpages5
dc.source.volume225
dc.subject.keywordsTRANSISTORS
dc.title

Heat-path layout technique for thermal mitigation in advanced CMOS technologies

dc.typeJournal article
dspace.entity.typePublication
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