Publication:

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

Date

2018
Proceedings Paper
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dc.contributor.authorPosthuma, Niels
dc.contributor.authorYou, Shuzhen
dc.contributor.authorStoffels, Steve
dc.contributor.authorLiang, Hu
dc.contributor.authorZhao, Ming
dc.contributor.authorDecoutere, Stefaan
dc.contributor.imecauthorPosthuma, Niels
dc.contributor.imecauthorYou, Shuzhen
dc.contributor.imecauthorStoffels, Steve
dc.contributor.imecauthorLiang, Hu
dc.contributor.imecauthorZhao, Ming
dc.contributor.imecauthorDecoutere, Stefaan
dc.contributor.orcidimecPosthuma, Niels::0000-0002-6029-1909
dc.contributor.orcidimecZhao, Ming::0000-0002-0856-851X
dc.contributor.orcidimecDecoutere, Stefaan::0000-0001-6632-6239
dc.date.accessioned2021-10-26T01:30:58Z
dc.date.available2021-10-26T01:30:58Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31558
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8393634/
dc.source.beginpage188
dc.source.conferenceIEEE 30th International Symposium on Power Semiconductor Devices and ICs - ISPSD
dc.source.conferencedate13/05/2018
dc.source.conferencelocationChicago, IL USA
dc.source.endpage191
dc.title

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

dc.typeProceedings paper
dspace.entity.typePublication
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