Low-frequency noise assessment on vertically stacked Si n-channel nanosheet FETs with different metal gates

dc.contributor.author	de Oliveira, Alberto
dc.contributor.author	Veloso, Anabela
dc.contributor.author	Claeys, Cor
dc.contributor.author	Horiguchi, Naoto
dc.contributor.author	Simoen, Eddy
dc.contributor.imecauthor	Veloso, Anabela
dc.contributor.imecauthor	Horiguchi, Naoto
dc.contributor.imecauthor	Simoen, Eddy
dc.contributor.orcidimec	Horiguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimec	Simoen, Eddy::0000-0002-5218-4046
dc.date.accessioned	2021-10-28T21:03:29Z
dc.date.available	2021-10-28T21:03:29Z
dc.date.issued	2020
dc.identifier.issn	0018-9383
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/34987
dc.identifier.url	https://ieeexplore.ieee.org/document/9205835
dc.source.beginpage	4802
dc.source.endpage	4807
dc.source.issue	11
dc.source.journal	IEEE Transactions on Electron Devices
dc.source.volume	67
dc.title	Low-frequency noise assessment on vertically stacked Si n-channel nanosheet FETs with different metal gates
dc.type	Journal article
dspace.entity.type	Publication
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