Backside Power Delivery: Game Changer and Key Enabler of Advanced Logic Scaling and New STCO Opportunities

Abstract

We report on devices built with the power delivery network (PDN) moved to the wafer’s backside (BS) for lower IR drop and improved routing efficiency. This concept can be implemented by differentiated schemes, some of which can be combined for 3D stacked structures such as CFET, and with Buried Power Rail (BPR) connected via scaled nTSV to BSM1 used for a first experimental demonstration. Device fabrication starts with frontside (FS) processing, after which the wafers are flipped over, bonded to carrier wafers and continued for the BS flow. Robust extreme wafer thinning has been achieved with a SiGe-Etch Stop Layer (ESL) added early on the FS, without impacting device properties. Optimized post-BS anneal(s) are shown to be effective for VT recovery (as some depassivation may occur after FS process), yielding improved mobility, DC performance, reliability and noise behavior. A scenario where the device’s source (S) is directly contacted from the BS (BSC-S) offers higher cell’s scalability potential, with stress, contact resistance, thermal (chip vs. transistor level, focus on hotspots) aspects assessed for various configurations. Its intrinsic S/D asymmetric access can also be explored to obtain low IOFF for small bandgap Ge/SiGe FETs. Further exploration work shows clear benefits for ESD diodes with BS contacts and for clock distribution implemented with (partial) BS routing, paving the way to a truly functional BS and new STCO opportunities.