Reliability in through silicon vias (TSVs)

Abstract

Through silicon vias (TSVs) are key enablers of the next generation of microelectronic products. TSVs are holes through the silicon substrate, filled with a metal, forming vertical conductors between the backside and the frontside of the die. In the last 10 years, TSV dimensions have been strongly decreased, and their diameters are now reaching sub-micrometer dimensions, with aspect ratios just below 10. In this article, multiple sources of reliability concerns will be reviewed. First of all, the reliability of the liner/barrier system will be addressed. The difficulty to obtain full sidewall coverage, due to high aspect ratios, small via diameters or etch topography, and its impact on reliability will be demonstrated. Furthermore, the need to optimize the etch recipe to avoid copper sputtering leading to poisoning of the liner will be clarified. Finally, the electromigration performance of the TSVs will be discussed.