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Design technology co-optimization for a robust 10nm solution for logic design and Sram

Date

2014
Proceedings Paper
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dc.contributor.authorVandewalle, Boris
dc.contributor.authorChava, Bharani
dc.contributor.authorSakhare, Sushil
dc.contributor.authorRyckaert, Julien
dc.contributor.authorDusa, Mircea
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorDusa, Mircea
dc.date.accessioned2021-10-22T07:31:16Z
dc.date.available2021-10-22T07:31:16Z
dc.date.embargo9999-12-31
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24732
dc.identifier.urlhttp://spie.org/Publications/Proceedings/Paper/10.1117/12.2048079
dc.source.beginpage90530Q
dc.source.conferenceDesign-Process-Technology Co-Optimization for Manufacturability VIII
dc.source.conferencedate25/02/2014
dc.source.conferencelocationSan Jose, CA USA
dc.title

Design technology co-optimization for a robust 10nm solution for logic design and Sram

dc.typeProceedings paper
dspace.entity.typePublication
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